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Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 9, September 2016

High Speed, Low Power Vedic Multiplier Using Reversible Logic Gate

Sonali S. Kothule | Shekhar H. Bodake ^[2]

Abstract: Multipliers are very significantpart of any processor or computing device. More often than not, performance of microcontrollers and DSP processors are calculated on the basis of number of multiplications completed in unit time. Therefore better multiplier architectures are assured to increase the capability of the device. Vedic multiplier is one such auspicious solution. Its easy architecture joined with raised speed forms an unparalleled combination for serving any composite multiplication computations. Attached with these best parts, realizing this with reversible logic further decreases power dissipation. Power dissipation is alternative significant constraint in an embedded system that cannot be ignored. In this paper we introduce a Vedic multiplier known as UrdhvaTiryakbhayam, realized by reversible logic that is the first of its kind. This multiplier may find applications in Fast Fourier Transforms, and additional applications of DSP like software defined radios, imaging, wireless communications.

Keywords: Vedic multiplier, Urdhva Triyagbhyam, Reversible logic, power, delay

Edition: Volume 5 Issue 9, September 2016,

Pages: 570 - 573