Comparative Analysis of D Flip-Flops in Terms of Propagation Delay

Anu Samanta, Madhu Sudan Das

Abstract: In this paper implementations of the flip-flops are presented which are positive edge triggered using 250 nm CMOS technology. The gate sizes are optimized precisely for low propagation delay without affecting the basic operation of flip-flops with a supply voltage of 5V. There are three important factors in CMOS i. e. the gate size area, power dissipation and speed of operation which always compromise between them when it is implemented in the field of IC circuit design. This paper proposes high speed design of D Flip-Flops in compared to the existing D flip-flops in terms of its area, aspect ratio, transistor count and propagation delay with the schematic and simulation results in Tanner tool version 16.

Keywords: CMOS, D Flip-Flops, Propagation Delay, Transistor count, W/L ratio