Clock Gating Based Low Power ALU Design
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 133 | Views: 335

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015 | Popularity: 6.2 / 10


     

Clock Gating Based Low Power ALU Design

M. Devendra, M. Naresh


Abstract: In this paper, latch based clock gating technique is applied in ALU to reduce clock power and dynamic power consumption of ALU. This technique is simulated in Xilinx14.7 tool and implemented on 90-nm sparton-3 FPGA. When clock gating technique is not applied clock power contributes 50 %, 41.46 %, 51.30 %, 55.15 and 55.78 % of overall dynamic power on 100MHz, 1GHz, 10GHz, 100GHz and 1THz device frequency respectively. When latch free clock gating technique is applied clock power contributes 17.85 %, 23.39 %, 26.49 % and 27.19 % of overall dynamic power on 100MHz, 1GHz, 10GHz, 100GHz and 1THz device frequency respectively. When latch based clock gating technique is applied clock power contributes 15 %, 17.89 %, 20 % and 21.56 % of overall dynamic power on 100MHz, 1GHz, 100GHz and 1THz device frequency respectively. When we use clock gating, there are 72.76 % reduction in clock power, 38.88 % reduction in IOs power and 44 % reduction in dynamic power in compare to power consumption without using clock gating technique. Clock gating saves power but increases over all area. There is 32.34 %, 37 %, 43.34 % and 44 % reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.


Keywords: Clock Gating CG, Latch free clock gating, Latch based clock gating, Low power, Dynamic power


Edition: Volume 4 Issue 8, August 2015


Pages: 341 - 345



Make Sure to Disable the Pop-Up Blocker of Web Browser


Text copied to Clipboard!
M. Devendra, M. Naresh, "Clock Gating Based Low Power ALU Design", International Journal of Science and Research (IJSR), Volume 4 Issue 8, August 2015, pp. 341-345, https://www.ijsr.net/getabstract.php?paperid=30071504, DOI: https://www.doi.org/10.21275/30071504

Similar Articles

Downloads: 107

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 3321 - 3325

Comparative Study on Logic Gates Using Bulk Transmission Gate and Double Gate Transmission Gate

Sima Baidya, Arindam Chakraborty

Share this Article

Downloads: 107

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 2162 - 2166

A Review of Embedded Base Power Management Unit

Utsava Khare, Megha Gupta

Share this Article

Downloads: 108

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 2425 - 2430

Implementation of Core-Lock Mechanism as A Data Synchronization Method in Embedded Multi-Core Systems

Megha.S, Dr C R Byrareddy

Share this Article

Downloads: 108 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh, Dr. Subodh Wairya

Share this Article

Downloads: 109

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article
Top