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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015

Clock Gating Based Low Power ALU Design

M. Devendra | M. Naresh

Abstract: In this paper, latch based clock gating technique is applied in ALU to reduce clock power and dynamic power consumption of ALU. This technique is simulated in Xilinx14.7 tool and implemented on 90-nm sparton-3 FPGA. When clock gating technique is not applied clock power contributes 50 %, 41.46 %, 51.30 %, 55.15 and 55.78 % of overall dynamic power on 100MHz, 1GHz, 10GHz, 100GHz and 1THz device frequency respectively. When latch free clock gating technique is applied clock power contributes 17.85 %, 23.39 %, 26.49 % and 27.19 % of overall dynamic power on 100MHz, 1GHz, 10GHz, 100GHz and 1THz device frequency respectively. When latch based clock gating technique is applied clock power contributes 15 %, 17.89 %, 20 % and 21.56 % of overall dynamic power on 100MHz, 1GHz, 100GHz and 1THz device frequency respectively. When we use clock gating, there are 72.76 % reduction in clock power, 38.88 % reduction in IOs power and 44 % reduction in dynamic power in compare to power consumption without using clock gating technique. Clock gating saves power but increases over all area. There is 32.34 %, 37 %, 43.34 % and 44 % reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.

Keywords: Clock Gating CG, Latch free clock gating, Latch based clock gating, Low power, Dynamic power

Edition: Volume 4 Issue 8, August 2015,

Pages: 341 - 345