Single Phase Clock Distribution using Low Power VLSI Technology

Krishna Naik Dungavath, Dr V. Vijayalakshmi

Abstract: Normally the clock distribution network will consume about 70 % of the total power consumed by the IC because this is the only signal which has the highest activity. Basically for a multi clock domain network we develop a multiple PLL to cater the need, but it consumes more power. So, the main aim of this project is developing a low power single clock multiband network which will supply for the multi clock domain network. It is highly useful and recommended for communication applications like Bluetooth, Zigbee, and WLAN. It is modeled using Verilog simulated using Modelsim and implemented in Xilinx.

Keywords: Prescaler, PLL, Programmable Counter, Swallow Counter, MOD, sel, clk, MC