International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 125 | Views: 197

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015


FPGA Implementation of SRRC Filter for WCDMA Systems

K. Pavan Kumar | Sri T. Thammi Reddy


Abstract: This paper presents the FPGA implementation of Square root raised cosine filter for pulse shaping used in WCDMA systems. Square root raised cosine filter is a FIR filter. Square root raised cosine filters are used in both transmitter and receiver for matching filter purpose. Mainly square root raised cosine filter is used for pulse shaping so that it reduces the required system bandwidth and also reduces inter symbol interference. SRRC filter also designed to maintain the power level in dbs. SRRC filter is designed by five levels of adders with a roll off factor 0.2. Shifting and add method is used for designing of SRRC filter.


Keywords: SRRC filter, FIR filter, Inter symbol interference, Pulse shaping, Roll off factor, WCDMA systems


Edition: Volume 4 Issue 7, July 2015,


Pages: 2581 - 2584


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