Modified Booth Multiplier with FIR Filter

B. Sireesha, Diana Aloshius

Abstract: In this paper, we develop a new methodology for designing a lower-error and area efficient 2s complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error compensation bias is realizable, constructing low-error fixed width Booth multiplier is area and time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to FIR filter. The simulation results show that the performance is superior than by using the direct-truncation fixed-width Booth multiplier.

Keywords: Modified Booth Multiplier, Booth Encoder, partial product, FIR, Signed-unsigned

How to Cite?: B. Sireesha, Diana Aloshius, "Modified Booth Multiplier with FIR Filter", Volume 3 Issue 3, March 2014, International Journal of Science and Research (IJSR), Pages: 798-802, https://www.ijsr.net/getabstract.php?paperid=26031406, DOI: https://dx.doi.org/10.21275/26031406

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