Design of E2 Framer and Deframer

C. Sudhakar, Sri M. Madhu Babu

Abstract: This paper describes the design and implementation of E1 frame and generating E2 frame multiplexing of 4 E1 Frames, as well as degenerating E1 frame from E2 frame. The design is implemented using Verilog HDL, functionally validated by simulation, carried out RTL and synthesized to get resource utilization and implemented on an FPGA for functionality verification, using Quartus II and Cyclone IV E FPGA family. The designed framer can be used for generation and analysis of E1 frame that has a data rate of 2.048 Mbps and E2 frame that has a data rate of 8.448 Mbps.

Keywords: E1 frame, CRC, clock divider, E2 frame, STM-1

How to Cite?: C. Sudhakar, Sri M. Madhu Babu, "Design of E2 Framer and Deframer", Volume 4 Issue 8, August 2015, International Journal of Science and Research (IJSR), Pages: 1846-1849, https://www.ijsr.net/getabstract.php?paperid=22081503, DOI: https://dx.doi.org/10.21275/22081503