Leakage Power Reduction in CMOS XOR Full Adder Using Power Gating With GDI Technique

Piyush Sharma, Ghanshyam Jangid

Abstract: As technology scales into the nanometre regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex arithmetic logic circuits. low leakage 1bit full adder cells are proposed for mobile application, gated-diffusion input (GDI) technique have been introduced for further reduction in power.

Keywords: Power gating, GDI, 1-bit full adder, Sequential circuit, sleep transistors

How to Cite?: Piyush Sharma, Ghanshyam Jangid, "Leakage Power Reduction in CMOS XOR Full Adder Using Power Gating With GDI Technique", Volume 3 Issue 8, August 2014, International Journal of Science and Research (IJSR), Pages: 1731-1733, https://www.ijsr.net/getabstract.php?paperid=2015837, DOI: https://dx.doi.org/10.21275/2015837

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