Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design

Vivek Dadheech, Ghanshyam Jangid

Abstract: This paper presents simultaneous use of clock gating and power gating in a sequential circuit, we have taken True Single Phase Clock (TSPC) FF. Clock gating is use to reduce the dynamic power whereas power gating technique is the best way to minimize the leakage current. If both the technique use in single circuit then we can minimize the power consumption and increase the performance of the circuit which also reduce the cost of the circuit, as also cost depends on the power consumption

Keywords: Clock gating, Power gating, TSPC FF, Sequential circuit

How to Cite?: Vivek Dadheech, Ghanshyam Jangid, "Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design", Volume 3 Issue 8, August 2014, International Journal of Science and Research (IJSR), Pages: 757-759, https://www.ijsr.net/getabstract.php?paperid=2015493, DOI: https://dx.doi.org/10.21275/2015493