Implementation of AES Algorithm in a Microblaze Processor Using System C

Rudo Duri, T. Madhavi Kumari

Abstract: This research investigates the Advanced Encryption Standard (AES) encryption and decryption algorithm with regard to 256- bit message length and 192- bit key length. In Spartan3 EDK we implemented the AES algorithm through pipelined architecture through the soft core processor, the Microblaze. Xilinx XC3S200 device of the Spartan family of the FPGA is used for hardware evaluation. The code is translated, mapped, placed and routed in Spartan 3 EDK using Xilinx Platform Studio (XPS). The microblaze processor is a RISC machine which is highly reconfigurable, uses 5-stage pipeline and has a 32-bit instruction word. By using system C coding the implementation makes it very low complexity architecture, that is, in saving the hardware resources. This implementation is most suited for hardware critical applications.

Keywords: AES encryption, decryption, XPS, microblaze processor, system C, FPGA, Spartan

How to Cite?: Rudo Duri, T. Madhavi Kumari, "Implementation of AES Algorithm in a Microblaze Processor Using System C", Volume 3 Issue 7, July 2014, International Journal of Science and Research (IJSR), Pages: 1815-1819, https://www.ijsr.net/getabstract.php?paperid=201537, DOI: https://dx.doi.org/10.21275/201537