Design of Modified Parallel Prefix Knowles Adder

Pawan Kumar, Jasbir Kaur

Abstract: Parallel Prefix Adders plays a prominent role in Digital Combinational Circuits. The basic function of adder in ALU is addition that is also used in Multipliers which results in decrease or increase of Delay that depends on the architecture of adder. Area and power are another important factors which really makes the adder effective The high performance digital adders with reduced area and low power consumption is an important design constraint for modern advanced processors. So, low power adders are also a need for todays VLSI industry. This Paper discusses the design of novel design of 16 bit Parallel Prefix adder. This adder is a mixture of two types of adders i. e Brent Kung and Knowles adder. At last there is comparison of 8 and 16 bit Knowles, 8 and 16 bit Modified knowles adder that is our Proposed design our design shows better performance from that of parallel prefix knowles and kogge stone adder in terms of power, area and Combinational path delay.

Keywords: Modified Knowles adder, carry look ahead adder, Knowles adder, Parallel Prefix adder

How to Cite?: Pawan Kumar, Jasbir Kaur, "Design of Modified Parallel Prefix Knowles Adder", Volume 3 Issue 7, July 2014, International Journal of Science and Research (IJSR), Pages: 199-201, https://www.ijsr.net/getabstract.php?paperid=2014908, DOI: https://dx.doi.org/10.21275/2014908