Verification of I2C Master Core using SystemVerilog-UVM

T Tarun Kumar, CY Gopinath

Abstract: This paper contracts the reusability of the I2C Bus protocol under various design environments; and by following Universal Verification Methodology (UVM) we can test the design and its functionality in these environments. The RTL design of I2C is open source and is obtained from Opencore. org; and its functional verification is carried by self; using SystemVerilog and UVM. The main advantage of this type of methodology is it does not interfere with the DUT and it is reusable with little or no modification. The design and verification in UVM is carried out on Mentor Graphics Questasim 10c. The coverage so obtained is 100 % for assertion based coverage and 90.15 % functional coverage using SV (SystemVerilog). The total coverage so obtained is 95.07 %.

Keywords: I2C, SystemVerilog, UVM, Functional Verification, Coverage, Assertion

How to Cite?: T Tarun Kumar, CY Gopinath, "Verification of I2C Master Core using SystemVerilog-UVM", Volume 3 Issue 6, June 2014, International Journal of Science and Research (IJSR), Pages: 2042-2046, https://www.ijsr.net/getabstract.php?paperid=2014676, DOI: https://dx.doi.org/10.21275/2014676