International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

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Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

A 3-Stage Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

Harshitha S [2] | Gopalakrishna K

Abstract: The discrete wavelet transform is used extensively in many fields, such as pattern recognition, image compression, speech analysis etc. because of its capability of decomposing a signal at multiple resolution levels. The 2-D Discrete Wavelet Transform is an operation through which a 2-D signal is successively decomposed in a spatial multi resolution domain by using low pass and high pass FIR filters along each of the dimensions. In this paper, we design and propose a scheme for high speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform. Here the main focus is to develop an architecture that provides a high operating frequency and a small number of clock cycles along with efficient hardware utilization. This is done by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is improved by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and then synchronizing their operations. The intra-stage parallelism is improved by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel. In order validate the proposed scheme, the code is written for 8x8 input values, simulated, and implemented in FPGA for the 2-D DWT computation.

Keywords: Discrete wavelet transform, pattern recognition, FIR filter, parallel architecture, field programmable gate array

Edition: Volume 3 Issue 7, July 2014,

Pages: 1391 - 1397

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