Low Power Circuit Design Using Positive Feedback Adiabatic Logic

Arjun Mishra, Neha Singh

Abstract: This paper presents an adiabatic logic family called positive feedback adiabatic logic circuits (PFAL). There is power reduction due to energy recovery in the recovery phase of the clock supply. The power dissipation comparison with the static CMOS logic is performed. The simulation is performed on cadence virtusuo using 180nm CMOS technology. The result shows that power reduction of 50 % to 70 % can be achieved over static CMOS within a practical operating frequency range.

Keywords: Adiabatic, CMOS, PFAL, ECRL, N-MOS, P-MOS

How to Cite?: Arjun Mishra, Neha Singh, "Low Power Circuit Design Using Positive Feedback Adiabatic Logic", Volume 3 Issue 6, June 2014, International Journal of Science and Research (IJSR), Pages: 43-45, https://www.ijsr.net/getabstract.php?paperid=2014110, DOI: https://dx.doi.org/10.21275/2014110