Design of Low Power Novel Viterbi Decoder Using Multiple Threshold CMOS Logic

B. Vijayapriya, B. M. Prabhu

Abstract: In this paper a low power viterbi decoder based on multiple threshold CMOS logic is presented. In wireless communication, viterbi decoder which consumes more power plays an important role. viterbi decoder is used to decode the received data which is encoded using convolution codes. In this paper in order to reduce the power consumption and to improve the performance of the decoder optimized gate logic is proposed. As the multiplexer and flip- flops are the major parts in the viterbi decoder circuit, multiple threshold CMOS (MTCMOS) logic is used to reduce the complexity of the circuit. The proposed technique is simulated using tanner tool. The simulated result shows the power consumption of viterbi decoder using MTCMOS is lower compared to CMOS logic and also the number of transistors required to design the viterbi decoder is reduced using MTCMOS logic.

Keywords: Viterbi decoder, multiple thresholds, tanner tool

How to Cite?: B. Vijayapriya, B. M. Prabhu, "Design of Low Power Novel Viterbi Decoder Using Multiple Threshold CMOS Logic", Volume 3 Issue 2, February 2014, International Journal of Science and Research (IJSR), Pages: 392-396, https://www.ijsr.net/getabstract.php?paperid=2013990, DOI: https://dx.doi.org/10.21275/2013990