Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology
Abstract: Analog to Digital Converter (ADC) is developed for operating at ultra low supply votages. Circuit is realized in 180 nm CMOS technology. The pre-simulation of ADC has been achieved on Caadence Virtuoso. The purpose of this work to develope a biomedical application. The research is focused on the design of ADC with sampling rate 100KS/s. It has very low cost and high speed technology with relative medium resolution and accuracy. This implies it posseses a good trade off between speed and cost. R2R DAC is used with a different approch in which matching of resistors is more easier than a conventional ADC.
Keywords: Cadence, CMOS, DAC, Sampling rate, VLSI
How to Cite?: Harshit Dosi, Rekha Agrawal, "Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology", Volume 2 Issue 7, July 2013, International Journal of Science and Research (IJSR), Pages: 417-418, https://www.ijsr.net/getabstract.php?paperid=02013184, DOI: https://dx.doi.org/10.21275/02013184