ASIC Implementation and Comparison of Diminished-one Modulo 2n+1 Adder
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 6, June 2017

ASIC Implementation and Comparison of Diminished-one Modulo 2n+1 Adder

Raj Kishore Kumar, Vikram Kumar

Modulo 2n+1 adder is one of the most common adder which have frequent use in RNS operations that has significant critical path, and often encountered in applications like pseudo-random number generation and cryptography as well. In this paper we have presented various types of diminished-one modulo 2n+1 adder using globular carry selection (GCS) and several parallel prefix adders. The adder has been simulated using verilog HDL codes and mapped this design to the TSMC (90 nm) and calculated the area, power dissipation and time for n= 8, 16, 32 & 64 and shown in the graph that which adder will have better power efficiency and time delay. Area occupied by several bits is presented in the table.

Keywords: RNS, Parallel Prefix Adder, GCS, ASIC

Edition: Volume 6 Issue 6, June 2017

Pages: 2826 - 2832

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How to Cite this Article?

Raj Kishore Kumar, Vikram Kumar, "ASIC Implementation and Comparison of Diminished-one Modulo 2n+1 Adder", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20172442, Volume 6 Issue 6, June 2017, 2826 - 2832

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