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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014
Power Reduction Approach in Combinational Circuit (Half and Full Subtractor)
Navendra Rawat | Rakesh Jain [6]
Abstract: The increasing market of mobile devices and battery operated portable electronic systems has led to the demands for chips that consume smallest possible amount of power and equally having high chip density and high throughput during recent years. The purpose of this design is to develop a subtractor circuit that meets the requirement for minimum power dissipation as well as not growing too much in size but if possible than minimize the size too. These goals are achieved using and comparing different techniques including alternate design for AND function. The other two techniques are Drain Gating and LECTOR.
Keywords: Standby power dissipation, Subtractor, Drain gating, Lector
Edition: Volume 3 Issue 7, July 2014,
Pages: 1104 - 1108
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Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014
Pages: 925 - 929Area and Delay Analysis of Modulo 2n ± 1 Adder Subtractor Using Prefix Adder on Weighted One and Diminished-1
Kishore Kunal | Ghanshyam Jangid [6]
Downloads: 114
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014
Pages: 563 - 567VLSI Implementation of Parallel Prefix Subtractor using Modified 2's Complement Technique and BIST Verification using LFSR Technique
Malti Kumari | Vipin Gupta [2] | Gaurav K Jindal