Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014
Area and Delay Analysis of Modulo 2n ± 1 Adder Subtractor Using Prefix Adder on Weighted One and Diminished-1
Kishore Kunal | Ghanshyam Jangid 
Abstract: Arithmetic architectures for modulo 2n+1 and 2n-1 adders and Subtractor are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n + 1 and 2n-1 addition. Second is Apart from addition a 2s compliment methodology has been introduced fro subtraction concept. The results are focusing on area and timing delay. These results is also being comparing in diminished-1 and weighted one for the individually adder and Sub-tractor and, while maintaining a high operation speed.
Keywords: Residue number system, Parallel Algorithm, Modular arithmetic, Weighted one, diminished-1
Edition: Volume 3 Issue 7, July 2014,
Pages: 925 - 929
How to Cite this Article?
Kishore Kunal, Ghanshyam Jangid, "Area and Delay Analysis of Modulo 2n ± 1 Adder Subtractor Using Prefix Adder on Weighted One and Diminished-1", International Journal of Science and Research (IJSR), Volume 3 Issue 7, July 2014, pp. 925-929, https://www.ijsr.net/get_abstract.php?paper_id=20141115
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