Design of Loop Filter Using CMOS
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

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Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 9, September 2013

Design of Loop Filter Using CMOS

Sanchita Basu

An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.

Keywords: Loop filter, CMOS, Low Pass Filter, VCO, Gain

Edition: Volume 2 Issue 9, September 2013

Pages: 284 - 287

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How to Cite this Article?

Sanchita Basu, "Design of Loop Filter Using CMOS", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=13091301, Volume 2 Issue 9, September 2013, 284 - 287

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