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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014
Pages: 563 - 567VLSI Implementation of Parallel Prefix Subtractor using Modified 2's Complement Technique and BIST Verification using LFSR Technique
Malti Kumari, Vipin Gupta, Gaurav K Jindal
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