Reduction of Static Power Dissipation in CMOS Inverter using Extra Nodes and Substrate Current

Harigovind, Sarath Mohan KP, Mariya Stephen

Abstract: Comparator is one of the fundamental building blocks in most analog to digital (ADC). Hence its fast operation at low voltage is very essential but without diminishing it performance. The issue related with using low supply voltage is reduced common mode input range. To enhance this techniques like supply boosting, usage of body driven transistors etc are used. Though all have certain advantages but the speed of the comparator was not reliable using any of these techniques. An additional circuitry is added to conventional dynamic comparator which takes care of this speed reliability. But the additional circuitry mismatch when solved gives the double tail comparator. Without complicating the design by adding few transistors a positive feedback is given to reduce the delay time. Many comparator architectures and its comprehensive delay analysis are discussed in this paper along with a new structure for double tail comparator without stacking too many transistors. The comparison between conventional dynamic comparator and double tail comparator is discussed further with its delay analytical expressions.

Keywords: Double tail comparator, kickback noise, dynamic clocked comparators, low power analog-digital convertors ADCs

How to Cite?: Harigovind, Sarath Mohan KP, Mariya Stephen, "Reduction of Static Power Dissipation in CMOS Inverter using Extra Nodes and Substrate Current", Volume 4 Issue 9, September 2015, International Journal of Science and Research (IJSR), Pages: 296-300, https://www.ijsr.net/getabstract.php?paperid=SUB157979, DOI: https://dx.doi.org/10.21275/SUB157979