International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064




Downloads: 118 | Views: 200

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015 | Rating: 6.8 / 10


Area-Delay-Power Efficient Carry-Select Adder

Shruthi Nataraj | Karthik.L


Abstract: This paper proposes on the logic operations in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC) -based CSLA to study the data dependency and to identify redundant logic operations. The new logic formulations have been proposed by eliminating all the redundant logic operations present in conventional CSLA. In the proposed scheme, the carry-select operation is scheduled before calculation of the final-sum. Anticipating carry-words (corresponding to Cin=0 and 1) and fixed Cin bits are the two Bit- patterns used for logic optimization of carry-select and general units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the proposed BEC-based CSLA. Due to small carry-output delay, the proposed CSLA design is good for square root (SQRT) -CSLA. As per the theoretical estimation the proposed SQRT-CSLA involves nearly 35 % less area-delay-product (ADP) than the BEC-based SQRT-CSLA which is the best amongst the existing SQRT-CSLA designs on average for different bit-widths. FPGA synthesis result shows that, the BEC-based SQRT-CSLA design involves more Area-Delay Product and consumes more energy than the proposed SQRT-CLSA on average for different bit-widths.


Keywords: Adder, BEC, Arithmetic unit, Area-Delay Product, MSB, Low power design


Edition: Volume 4 Issue 6, June 2015,


Pages: 222 - 226


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