International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 106 | Views: 233

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015 | Rating: 6.4 / 10

Design and Implementation of 64-Bit Multiplier Using CLAA and CSLA

Shaik Meerabi | Krishna Prasad Satamraju

Abstract: This paper deals with comparative study of the Carry Look-Ahead Adder (CLAA) based 64-bit unsigned integer multiplier and Carry Select Adder (CSLA) based 64-bit unsigned integer multiplier. Multiplication is a fundamental operation in most of the signal processing algorithms. Multipliers occupy large area, long latency and consume considerable power. Therefore there is a need for designing a multiplier that consumes less power. Moreover the digital systems efficiency is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system, and consumes more area. Hence, optimizing the speed, area and delay of the multiplier is a major design issue. Carry Select Adder (CSLA) is one of the fastest adders used in many applications to perform fast arithmetic functions. From the structure CSLA there is a scope for reducing area and delay by using Common Boolean Logic (CBL). This work evaluates the performance of the proposed designs in terms of area, delay, and power. The power dissipation is same for both CLAA based multiplier and CSLA based multiplier. But the area delay product of modified CSLA based multiplier is reduced to 6 % when compared to CLAA based multiplier. These multipliers are simulated and synthesized using Modelsim6.4b and Xilinx 10.1.

Keywords: CLAA, CSLA, CBL, Delay, Area

Edition: Volume 4 Issue 2, February 2015,

Pages: 2242 - 2245

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