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Comparative Study | Electronics Engineering | Volume 15 Issue 5, May 2026 | Pages: 1837 - 1842 | India
Implementation of Tomasulo Algorithm for Out-of-Order Execution of Risc-V Processor
Abstract: Modern high-performance processors extensively utilize out-of-order execution to overcome data and control hazards, thereby maximizing instruction-level parallelism (ILP). These abstract outlines the implementation of a microarchitectural design incorporating the Tomasulo algorithm for out-of-order execution within a pipelined RISC-V processor. The RISC-V Instruction Set Architecture (ISA), with its modularity and open-source nature, provides an ideal platform for exploring advanced microarchitectural concepts. The objective of this implementation is to demonstrate how the Tomasulo algorithm effectively manages data dependencies, minimizes pipeline stalls, and improves overall throughput by allowing instructions to execute as soon as their operands are available, rather than strictly adhering to program order. An Instruction Fetch and decode Unit, Reorder Buffer, Register Renaming, Functional Units, Reservation Stations and Common Data Bus are implemented in this project. The execution flow of an instruction within this Tomasulo implementation for RISC-V proceeds as follows: Instructions are fetched and decoded. If a functional unit is available and its corresponding reservation station has space, the instruction is issued. Operands are fetched from the Register File or awaited from the CDB. Once all operands are ready, the instruction executes in its respective functional unit. Upon completion, the result is broadcast on the CDB, allowing dependent instructions in reservation stations and the ROB to update their operand values. Finally, instructions commit their results from the ROB to the Register File or memory in program order, ensuring architectural correctness. This out-of-order, in-order commit strategy, enabled by the Tomasulo algorithm, significantly enhances the performance of a RISC-V processor by dynamically scheduling instruction execution based on data availability, thereby maximizing the utilization of functional units and mitigating the impact of pipeline stalls due to data dependencies.
Keywords: Tomasulo algorithm, RISC-V, Reorder buffer, Reservation Stations
How to Cite?: Dr. Manjula G, Akshatha Gowda A, Bhargavi G, Deekshitha G C, Kajol Prasad P, "Implementation of Tomasulo Algorithm for Out-of-Order Execution of Risc-V Processor", Volume 15 Issue 5, May 2026, International Journal of Science and Research (IJSR), Pages: 1837-1842, https://www.ijsr.net/getabstract.php?paperid=SR26529123710, DOI: https://dx.dx.doi.org/10.21275/SR26529123710