Reduction of Leakage Power for VLSI Design Logic Gate Circuits

Kiran Renukuntla

Abstract: High power dissipation has become key role in VLSI design circuits, when it comes to battery - operated applications it is important to save the battery life. Short - circuit power and switching power play key role in power dissipations, there are so many techniques to reduce power. By stacking arrangement, we can reduce power and we can utilize technique for various circuits. In this paper NAND and NOR gates realized, stacking technique consumes low power than standard reduction techniques. These circuits are simulated in Tanner EDA Tool with generic 250 nm transistors.

Keywords: NAND gate, NOR gate, Leakage Power, STACK, CMOS Transistor

How to Cite?: Kiran Renukuntla, "Reduction of Leakage Power for VLSI Design Logic Gate Circuits", Volume 12 Issue 3, March 2023, International Journal of Science and Research (IJSR), Pages: 470-472, https://www.ijsr.net/getabstract.php?paperid=SR23310223015, DOI: https://dx.doi.org/10.21275/SR23310223015