International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 4 | Views: 156 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper | Electronics & Communication Engineering | India | Volume 11 Issue 10, October 2022 | Rating: 4.6 / 10


Implementation of Low Power Multiplier for High Speed Arithmetic Applications

Kishor Kanaparthi [2]


Abstract: In DSP and FPGA based applications power, speed and area all are important parameters and all are depend on multiplier which in turn depends on adders. So, by implementing adders we can reduce the delay. Pyramidaladders are used which uses half-adder and full-adder to increase the speed and to reduce the number of gates used in the multiplier, but delay is not decreased significantly. By using of modified half-adder and full-adder both gate count and delay is reduced normal to 16-bit multiplier. If we modify the Pyramidal adder with XNOR's and MUX instead of normal half-adder and full-adder, such pyramidal adder useless gates and delay is reduced compared normal 16-bit adder. The use of XNOR's and MUX in Pyramidal adder reduces delay, as the MUX function is only select the output among inputs. The use of such pyramidal adder in multiplier delay can be decreased greatly.


Keywords: multiplexer, FPGA, XOR, Carry Generator


Edition: Volume 11 Issue 10, October 2022,


Pages: 59 - 62


How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link


Verification Code will appear in 2 Seconds ... Wait

Top