International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 1 | Views: 69

Review Papers | Communication Engineering | India | Volume 11 Issue 5, May 2022


Enhanced Hamming Codes on SRAM based FPGA for Space Applications

Shahana .P .N


Abstract: Field Programmable Gate Arrays (FPGAs) are increasingly demanded by spacecraft electronic designers due to its improved performance. SRAM-based FPGAs are uniquely suited for remote missions? applications. But due to high radiation on the sensitive part of the circuits introduces soft errors, also called Single Event Upset (SEU). Radiation-induced soft error rate (SER) degrades the reliability of static random-access memory (SRAM)-based field programmable gate arrays (FPGAs). Error Correction Codes (ECCs) are used to prevent soft errors from causing data corruption in memories and registers. Highly preferred error detection technique is Triple Modular Redundancy (TMR). TMR comes with high area and power dissipation penalties. Most of the error detection and correction technique can correct errors by the entire reprogramming techniques. Hence affects the entire system functionality. This paper presents Enhanced Hamming codes on SRAM-based FPGAs in hostile operating environments such as space. This technique provides multibit error correction and adjacent error detection capability can improve the reliability, and hence, system availability, by orders of magnitude. Here we have 2D Hamming encoder section with selective bitplacement strategy and decoder section with lexicographic check matrix. Simulation results show that the multibit error correction capability of Enhanced hamming codes can recover configuration bits without depending on an external memory preserving a golden copy of the configuration bits. This multibit error correction technique provides higher FPGA system throughput and high error tolerance.


Keywords: FPGA (Field Programmable Gate Arrays), SEU (Single Event Upset), SER (Soft Error Rate), ECC (Error Correction Code), TMR (Triple Modular Redundancy), SRAM (Static Random Access Memory)


Edition: Volume 11 Issue 5, May 2022,


Pages: 1165 - 1169


How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link


Verification Code will appear in 2 Seconds ... Wait

Top