LDPC Minimum Sum Algorithm Decoder with Weight (3, 6) Regular Parity Check Matrix: A Review

Mamta Prakash, Girraj Prasad Rathore

Abstract: Low-Density parity-check (LDPC) codes are unit one in every of the foremost powerful error correcting codes obtainable nowadays. Their Shannon capability approaching performance and lower cryptography quality have created them the simplest choice for several wired and wireless applications. This paper offers a review on the one of the best technique for error detection and correction. The paper includes all the previous work related to the LDPC codes.

Keywords: LDPC, Decoder, Min-sum Algorithm, FPGA

How to Cite?: Mamta Prakash, Girraj Prasad Rathore, "LDPC Minimum Sum Algorithm Decoder with Weight (3, 6) Regular Parity Check Matrix: A Review", Volume 3 Issue 9, September 2014, International Journal of Science and Research (IJSR), Pages: 2033-2034, https://www.ijsr.net/getabstract.php?paperid=SEP14557, DOI: https://dx.doi.org/10.21275/SEP14557