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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014
An Efficient Low Latency Low Complexity Architecture for Matching of Information Coded with Error-Correcting Codes
Sankareswari.M | Udhayakumar.S
Abstract: A computing system is one, where an input data needs to be compared with a stored data to locate the matching entry, e. g. , translation look-aside buffer and cache tag array lookup matching. In this paper we propose a new architecture in to reduce complexity and latency for matching the data protected with an error-correcting code (ECC). It is based on the fact that the codeword of an ECC generated by encoding is usually represented in a systematic form, and it consists of the raw data and the parity information. The proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. The proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected.
Keywords: Data comparison, error-correcting codes ECCs, Hamming distance, tag matching, butterfly-formed weight accumulator BWA, Orthogonal Latin square OLS, Low density parity check LDPC
Edition: Volume 3 Issue 11, November 2014,
Pages: 2745 - 2749