International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 119 | Views: 294

Comparative Studies | Electronics & Communication Engineering | India | Volume 5 Issue 5, May 2016 | Popularity: 6.7 / 10


     

Comparison of Various Adder Designs in terms of Delay and Area

Khushboo Bais, Zoonubiya Ali


Abstract: VLSI designers are constantly working towards the optimization of speed, power, and area of circuits, but practically it is difficult to optimize all at the same time. This paper presents a comparative study of the designs of parallel adders- ripple carry adder, carry look-ahead adder and Kogge-Stone adder, which have been designed using Xilinx ISE 14.7 Design Suite and synthesized for Spartan 3 FPGA. All the adders have been designed for 4-bit, 8-bit, and 16-bit operands and a comparison of delay performance and area utilization has been made as per the data obtained from the synthesis results. The effect of parallelism on speed and area of adder designs has been analysed, and it has been observed that both the parameters cannot be optimized at the same time. If parallelism is increased in order to increase the speed of operation, then it will result in large area occupancy, and if area is to be optimized then we have to adjust with the slow speed of system.


Keywords: Ripple Carry Adder RCA, Carry Look-Ahead Adder CLA, Parallel Prefix Adders PPA, Xilinx ISE, Spartan 3


Edition: Volume 5 Issue 5, May 2016


Pages: 1292 - 1295


DOI: https://www.doi.org/10.21275/NOV163657



Make Sure to Disable the Pop-Up Blocker of Web Browser




Text copied to Clipboard!
Khushboo Bais, Zoonubiya Ali, "Comparison of Various Adder Designs in terms of Delay and Area", International Journal of Science and Research (IJSR), Volume 5 Issue 5, May 2016, pp. 1292-1295, https://www.ijsr.net/getabstract.php?paperid=NOV163657, DOI: https://www.doi.org/10.21275/NOV163657



Similar Articles

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

Downloads: 110

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2600 - 2606

Design and Implementation of Galios Field Based AES-256 Algorithm for Optimized Cryptosystem

Veerendra Babu Dara, P. Sankara Rao

Share this Article

Downloads: 114

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1955 - 1959

A High Quality Image Scaling Processor With Reduced Memory

Amal Mole.S, Sarath Raj.S

Share this Article

Downloads: 116

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2933 - 2937

Design and Analysis of Low Power High Speed Area Efficient Multipliers using Compressors on FPGA

Ch. Naga Srinivasa Rao, K. V. B. Chandra Sekhar Rao

Share this Article

Downloads: 116 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 12, December 2016

Pages: 1648 - 1652

Design and Implementation of High Performance Multiplier Using HDL

Prajakta P. Chaure, G. D. Dalvi

Share this Article
Top