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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 3, March 2016

Digital Signal Processing Applications using Multiplier Technique in Fixed Point Arithmetic

V. Indhumaraghathavalli | S. Rajan ^[3]

Abstract: - Embedded and mobile computing devices are frequently required to execute some key digital signal processing applications. Such applications using fixed point arithmetic for some computational errors. Most of the digital signal processing application required to increase the speed. In this proposed multipliers are array multipliers, Booth multipliers and Modified booth multipliers compared with their power, area and accuracy. Finally, note that the modified booth multiplier is improving the performance based on the power area and accuracy. But the delay is reduced in the Booth multiplier. The computation error is present in the multipliers, but it does not affect the quality of the DSP applications.

Keywords: fixed point, multipliers, multiplexers, truncation, power consumption

Edition: Volume 5 Issue 3, March 2016,

Pages: 993 - 996