Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes
Abstract: Low Density Parity Check (LDPC) technique is highly used in the communication protocol to effectively transfer data from transceiver end to receiver end. In this paper a highly efficient decoding technique viz. min-sum has used to transfer data. The data from the communication channel is used for the decoding process. Min-Sum algorithm decoder is implemented and simulation is done using Model sim. The hardware synthesis results are shown using Xilinx ISE 14.1 and Spartan 6 FPGA board.
Keywords: LDPC, Decoder, Min-sum Algorithm, FPGA
How to Cite?: Mamta Prakash, Girraj Prasad Rathore, "Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes", Volume 4 Issue 12, December 2015, International Journal of Science and Research (IJSR), Pages: 1451-1453, https://www.ijsr.net/getabstract.php?paperid=NOV152281, DOI: https://dx.doi.org/10.21275/NOV152281