Improved Architectures for Fused Floating Point Add-Subtract Unit

Pooja Potdar, S. S. Tamboli

Abstract: The fused floating point add-subtract unit is useful for digital signal processing (DSP) applications Such as fast Fourier transform (FFT) & discrete cosine transform (DCT) butterfly operations. To improve the performance of fused floating point add-subtract unit, a dual path algorithm & pipelining algorithms are useful. The designs are implemented for both single and double precision. The fused floating point add-subtract unit saves area and power consumption compared to discrete floating point add-subtract unit. The dual path design reduces latency compared to discrete design with area and power consumption between discrete and fused design. The fused dual path floating point add-subtract unit can be split into two pipeline stages, since latencies of two pipeline stages will be fairly well balanced.

Keywords: Digital signal processing DSP, Floating point arithmetic, Fused floating point operation, High speed computer arithmetic

How to Cite?: Pooja Potdar, S. S. Tamboli, "Improved Architectures for Fused Floating Point Add-Subtract Unit", Volume 4 Issue 12, December 2015, International Journal of Science and Research (IJSR), Pages: 496-498, https://www.ijsr.net/getabstract.php?paperid=NOV152018, DOI: https://dx.doi.org/10.21275/NOV152018