Review on Scalable FFT Architecture for High Speed Communication Standard

Rutuja C. Tamhane, Shrikant J. Honade

Abstract: The Fast Fourier transform (FFT) has presently a key role in signal processing applications. Most of the system needs high flexibility, high speed and high efficiency. The baseband hardware should be economical and capable enough to compute FFT within the time constraints necessary to support multiple wireless standards. Baseband hardware should be scalable so it supports multiple wireless standards as well as it should meet the performance constraints such as high speed, low area and low power consumption. Hence, the baseband hardware needs a scalable FFT module that meets the performance constraints required by multiple wireless standards. This paper presents a highly efficient hierarchical design of an application specific instruction set processor architecture exploration, software tools design, system verification and design implementation. Simulation and synthesis results show that our FFT-ASIP achieves a higher energy-efficiency and flexibility and the area cost will be low.

Keywords: Application-specific instruction set processor ASIP, fast Fourier transforms FFT, hierarchical design, TMS320C6X kit, code composer

How to Cite?: Rutuja C. Tamhane, Shrikant J. Honade, "Review on Scalable FFT Architecture for High Speed Communication Standard", Volume 4 Issue 11, November 2015, International Journal of Science and Research (IJSR), Pages: 1706-1708, https://www.ijsr.net/getabstract.php?paperid=NOV151544, DOI: https://dx.doi.org/10.21275/NOV151544

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