International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 128 | Views: 242

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015 | Rating: 6.6 / 10

Online Fault Detection, Diagnosis and Repair using RA

Ankita Tripathi

Abstract: Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test circuit itself. But for this circuit have to switch in off-line mode which unnecessary waste time and power to avoid this best method is online bist In this paper BIST architecture is implemented for Detection, Diagnosis and Repair of various faulty circuits. A complete and versatile online test solution based on reconfigurable test architecture is presented in this paper. Reconfigurable test architecture works alongside the controllers for online concurrent fault detection. The output vectors of the controllers are concurrently monitored and any fault present is detected in a few cycles from the sensitization of the fault. The architecture is then reprogrammed to a similar set of diagnostic hardware to locate a sub block which is the cause for the fault. The same architecture is then reprogrammed to replace the faulty block thereby completing repair. The test architecture is designed based on configurable logic blocks. The design has several advantages viz. (i) it works well for critical VLSI controllers where shutting down or suspending the operation of a controller for testing is not possible and where the fault needs to be detected at the earliest, during the run time of the system, (ii) after a fault is detected, diagnosis can be performed online, (iii) once a faulty block is located, repair is also done online. Since fault detection, diagnosis and repair are completed online with one test hardware, the effective hardware overhead is negligible and the system can resume its function within a brief period. The applicability of the architecture is demonstrated for the control blocks in OC8051.

Keywords: concurrent test, multiple controllers, online test, output vector monitoring, programmable architecture, reconfigurable architecture

Edition: Volume 4 Issue 11, November 2015,

Pages: 66 - 70

How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link

Verification Code will appear in 2 Seconds ... Wait