International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 127 | Views: 172

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015


Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic

Nadisha E B | Akhila P R


Abstract: This paper presents a low power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage is comprised of the logic function called efficient charge recovery logic (ECRL) gatesand a handshake controller. ECRL gates have negligible leakage power dissipation. By incorporatingpartial charge reuse (PCR) mechanism the energy dissipation required to complete the evaluation of an ECRL gate can be reduced. Moreover, AFPL-PCR adopts a C*-element, in its handshake controllers. To mitigate the hardware overhead of the AFPL circuit, circuit simplificationtechniques have been developed.


Keywords: AFPL circuits, CSLA adders, PCR mechanism, ECRL logic gates


Edition: Volume 4 Issue 11, November 2015,


Pages: 258 - 263


How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link


Verification Code will appear in 2 Seconds ... Wait

Top