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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 5, May 2017 | Popularity: 6.3 / 10
Design and Implementation of High Speed and Low Power Consumption FinFET
Ragini Soni, Jyotsna Sagar
Abstract: An application of FinFET Technology has opened new development in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects.
Keywords: DIBL, etches, FinFET, GIDL, hysteretic threshold, Mosfet
Edition: Volume 6 Issue 5, May 2017
Pages: 1133 - 1136
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Ragini Soni, Jyotsna Sagar, "Design and Implementation of High Speed and Low Power Consumption FinFET", International Journal of Science and Research (IJSR), Volume 6 Issue 5, May 2017, pp. 1133-1136, https://www.ijsr.net/getabstract.php?paperid=9051702, DOI: https://www.doi.org/10.21275/9051702