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Review Papers | Electronics Communication Engineering | Volume 5 Issue 1, January 2016 | Pages: 770 - 772 | India
VLSI Based Robust Router Architecture
Abstract: In this paper, we introduce networking solution by using VLSI architecture techniques to router design for networking system to provide control over the network. We attempts to overcome latency and time reduction issue and can provide multipurpose networking router by means of verilog and it was synthesized in Xilinx 13.2 version, simulated Modelsim 10.0 version. The approach enables the router to process mul-tiple incoming IP packets with different versions of protocols simultaneously, e. g. for IPv4 and IPv6.
Keywords: verifying Router Protocol Verilog
How to Cite?: Pramod Kulkarni, M. N. Karanjkar, "VLSI Based Robust Router Architecture", Volume 5 Issue 1, January 2016, International Journal of Science and Research (IJSR), Pages: 770-772, https://www.ijsr.net/getabstract.php?paperid=8011602, DOI: https://dx.doi.org/10.21275/8011602