Power Reduction Approach in Combinational Circuit (Half and Full Subtractor)
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 106 | Views: 323

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014 | Popularity: 6.1 / 10


     

Power Reduction Approach in Combinational Circuit (Half and Full Subtractor)

Navendra Rawat, Rakesh Jain


Abstract: The increasing market of mobile devices and battery operated portable electronic systems has led to the demands for chips that consume smallest possible amount of power and equally having high chip density and high throughput during recent years. The purpose of this design is to develop a subtractor circuit that meets the requirement for minimum power dissipation as well as not growing too much in size but if possible than minimize the size too. These goals are achieved using and comparing different techniques including alternate design for AND function. The other two techniques are Drain Gating and LECTOR.


Keywords: Standby power dissipation, Subtractor, Drain gating, Lector


Edition: Volume 3 Issue 7, July 2014


Pages: 1104 - 1108



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Navendra Rawat, Rakesh Jain, "Power Reduction Approach in Combinational Circuit (Half and Full Subtractor)", International Journal of Science and Research (IJSR), Volume 3 Issue 7, July 2014, pp. 1104-1108, https://www.ijsr.net/getabstract.php?paperid=20141188, DOI: https://www.doi.org/10.21275/20141188

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