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Comparative Studies | Electronics Communication Engineering | Volume 3 Issue 7, July 2014 | Pages: 764 - 767 | India
Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology
Abstract: Power consumption has emerged as a primary design constraint for today VLSI integrated circuits (ICs). AS per reducing Technology, mostly Nanometer technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU. In this paper we introduced low power consume one-bit full adders, including the most motivating of those are analyzed and compared for speed, leakage power, and leakage current. The simulation has been carried out on a Cadence environment virtuoso tool using a 0.45-m technology
Keywords: VLSI, CMOS, Full Adder, leakage current, process invariance and circuit invariance
How to Cite?: Umashankar Dhepra, Rajkumar Gehlot, "Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology", Volume 3 Issue 7, July 2014, International Journal of Science and Research (IJSR), Pages: 764-767, https://www.ijsr.net/getabstract.php?paperid=20141136, DOI: https://dx.doi.org/10.21275/20141136