International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014


Design and Implementation of Galios Field Based AES-256 Algorithm for Optimized Cryptosystem

Veerendra Babu Dara | P. Sankara Rao


Abstract: All of the cryptographic algorithms we have looked at so far have some problem. The earlier ciphers can be broken with ease on modern computation systems. As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations. As far as memory applications are concerned the soft errors and single event upsets are always a matter of problem. In this paper presents an optimized composite field arithmetic based S-Box implemented in four stage pipeline. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF (28) to GF (22) 2) 2), so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (1609/29504 Slices on a Spartan 3 XC3S1600E-4, fg484).


Keywords: Advanced Encryption Standard AES 4, Composite Field Arithmetic 3, Cryptography, Galios Field 1, 13, Memory, Xilinx ISE 121 Design suite and Verilog


Edition: Volume 3 Issue 11, November 2014,


Pages: 2600 - 2606


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