Ternary Logic Gates and Ternary SRAM Cell Implementation in VLSI

Punnam Nagaraju, Neerati Vishnuvardhan

Abstract: : This paper presents Very Large Scale Integration (VLSI) design and simulation of a ternary logic gates and CMOS ternary SRAM cell. The Simple Ternary Inverter, Positive Ternary Inverter and Negative Ternary Inverter are designed in 180nm technology. The Ternary NAND Gate and Ternary NOR Gate are also designed and simulated. The ternary SRAM consists of crosscoupled ternary inverters. SPICE simulations confirmed that the functional behavior of the READ and WRITE operations is correct

Keywords: Multiple-valued logic MVL, CMOS Ternary Logic, Ternary SRAM, Simple Ternary Inverter STI, Positive Ternary Inverter PTI, Negative Ternary Inverter NTI

How to Cite?: Punnam Nagaraju, Neerati Vishnuvardhan, "Ternary Logic Gates and Ternary SRAM Cell Implementation in VLSI", Volume 3 Issue 11, November 2014, International Journal of Science and Research (IJSR), Pages: 1920-1824, https://www.ijsr.net/getabstract.php?paperid=13111402, DOI: https://dx.doi.org/10.21275/13111402

Download Citation: APA | MLA | BibTeX | EndNote | RefMan