Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

K. Swarna Madhuri, M. Madhu Sudhan Reddy

Abstract: In this paper a new low power and high performance adder cell using a new design style called Bridge is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) and 180nm standard CMOS technology at room temperature, with supply voltage variation from 0.65v to 1.5v with 0.05v steps.

Keywords: CMOS Circuit, VLSI, Full adder, Bridge style

How to Cite?: K. Swarna Madhuri, M. Madhu Sudhan Reddy, "Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell", Volume 4 Issue 8, August 2015, International Journal of Science and Research (IJSR), Pages: 1101-1105, https://www.ijsr.net/getabstract.php?paperid=10081502, DOI: https://dx.doi.org/10.21275/10081502