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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 3, March 2016
VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers
L. Keerthana | M. Nisha Angeline [2]
Abstract: In many digital systems, the most important and basic component ismultiplier and adder which are recommended for implementing the concepts of DSP systems, arithmetic and logic functions and multimedia applications. In many real time digital applications, power dissipation and hardware size are the major constraints. In this paper, we propose a method that combines a numerical transformation called number splitting with a shift-and-add decomposition scheme. In this design NxN bit multiplication is done by using (N-1) x (N-1) bit multiplication. The weight reduction and redundant techniques are used to greatly reduce the strength of multiplication. Various multiplier designs are taken and they are compared based on their speed and area. The speed of the system is increased by reducing the size of the hardware, power consumption and path delay. The designs are modeled using VHDL and implemented in Xilinx Spartan FPGA.
Keywords: Numerical transformation, weight reduction, redundant technique, shift-and-add decomposition
Edition: Volume 5 Issue 3, March 2016,
Pages: 983 - 987
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Research Paper, Electronics & Communication Engineering, Nigeria, Volume 11 Issue 8, August 2022
Pages: 1164 - 1169Propagation Modelling and Propagation Loss Prediction using Wide-Angle Split-Step Fourier Transform Algorithm in Rain Medium
Godwin Effiong [2] | Tebe Larry Ojukonsin [2] | Ayibapreye Kelvin Benjamin [2]
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Research Paper, Electronics & Communication Engineering, Niger, Volume 11 Issue 9, September 2022
Pages: 522 - 527Evaluation of Split-Step Fourier Transform for Tropospheric Electromagnetic Wave Propagation
Godwin Effiong [2] | Tebe Larry Ojukonsin [2] | Ayibapreye Kelvin Benjamin [2]