M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 11, November 2017
A CMOS 3?12-GHz Ultra wideband Low Noise Amplifier by Dual-Resonance Network
Surabhi Katiyar, Bhawna Trivedi
A low-power and high power-gain (S21) ultra wide-band low noise amplifier (UWB LNA) with flat noise figure (NF) based on global foundries 0.13-m CMOS technology is reported. The load effect of common-gate (CG) topology is applied with dual-resonance load network for both wide band input matching and NF flatness. Combined with inductive-series peaking technique, the frequency response of CG-common-source cascade topology is further extended. The LNA circuit achieves the high and flat power gain of 13.5 1.5 dB with input return loss better than 13dB and a flat NF of 4.3 dB 0.4 dB for frequencies 3-12 GHz. The fabricated LNA occupies a die area of 1.09 0.8 mm2 including pads and draw 8.5 mW from 1.2 V dc supply.
Keywords: Common gate CG, common source CS, low noise amplifier LNA, matching network, ultra-wideband UWB
Edition: Volume 6 Issue 11, November 2017
Pages: 2152 - 2154
How to Cite this Article?
Surabhi Katiyar, Bhawna Trivedi, "A CMOS 3?12-GHz Ultra wideband Low Noise Amplifier by Dual-Resonance Network", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20178499, Volume 6 Issue 11, November 2017, 2152 - 2154