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Analysis Study Research Paper | Electrical & Electronics Engineering | India | Volume 9 Issue 8, August 2020 | Rating: 4.6 / 10
Automated Testing Framework for Functionality of Configuration of Complex Modern Architectures
Ankit Chandankhede
Abstract: Modern compute architectures have been architected to be scalable for different applications such as low power chips for mobile, wearable devices and high-performance chips for servers and scientific computers. The scalability and configurability of architecture and features [3] are controlled by the register writes through firmware and parameters to scale the design for instancing multiple pipelines or cores or cache size. Further register writes are also used for fallback option if a feature or fix does not function as expected. Hence verifying the register writes to enable such feature crossing with different design parameters becomes paramount of interest. The number of registers and combinations of parameters grows exponential for such architectural complexities. Thus, verification cycles can prolong and time to production can be exponentially large. This paper proposes an automated approach to randomly test the register combinations through stimulus along with design parameters by parsing feature and register documentations.
Keywords: scalable architectures, low power chips, high performance chips, register verification, automated testing
Edition: Volume 9 Issue 8, August 2020,
Pages: 1576 - 1579