A Review Study on High Speed Adder for Image Processing Applications

Parul Jaiswal, Rahul Gedam

Abstract: This paper is primarily deals the construction of 16 bit high speed on adder. The motivation behind the investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU). In this research article, we will present comparative analysis and study on existing 16 bit adder with some approximation technique which is used in arithmetic application. Here we discuss about the existing accurate and approximate architecture of different kind of adder. As we there is many application where accuracy can be tolerable by human eye. So there is no need of accurate design we can use approximate design for those kind of applications. This paper is implementing the existing design on Xilinx-14.2 and simulated is done on Modelsim. Key Index FPGA, LUT, ALU, CPU, ASIC, APPROXIMATION

Keywords: FPGA, LUT, ALU, CPU, ASIC, APPROXIMATION

How to Cite?: Parul Jaiswal, Rahul Gedam, "A Review Study on High Speed Adder for Image Processing Applications", Volume 4 Issue 5, May 2015, International Journal of Science and Research (IJSR), Pages: 2869-2874, https://www.ijsr.net/getabstract.php?paperid=SUB154896, DOI: https://dx.doi.org/10.21275/SUB154896