Implementation of AES Algorithm Using FPGA & Its Performance Analysis

Sonali A. Varhade, N. N. Kasat

Abstract: Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that is used to protect electronic data. The large and growing number of internet and wireless communication users has led to an increasing demand of security measures and devices for protecting the user data transmitted over the unsecured network so that unauthorized persons cannot access it. As we share the data through wireless network it should provide data confidentiality, integrity and authentication. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is advanced encryption standard (AES). AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has lot of advantage such has increased throughput and better security level. Hardware Implementation for 128 bit AES (Advanced Encryption Standard) encryption and Decryption has been made using VHDL. The proposed algorithm for encryption and decryption module functionally verified using modelsim and synthesize using Quartus 2 using Altera FPGA platform and analyze the design for the power, Throughput & area.

Keywords: AES, Encryption, Decryption, Security, FPGA, VHDL

How to Cite?: Sonali A. Varhade, N. N. Kasat, "Implementation of AES Algorithm Using FPGA & Its Performance Analysis", Volume 4 Issue 5, May 2015, International Journal of Science and Research (IJSR), Pages: 2484-2492, https://www.ijsr.net/getabstract.php?paperid=SUB154844, DOI: https://dx.doi.org/10.21275/SUB154844