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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015

Fully Reused VLSI Architecture of FM0/Manchester Encoding Technique for Memory Application

Triveni A Patil | Sadhana Choudhary ^[2]

Abstract: In this paper a fully reused VLSI architecture of FM0/Manchester encoding technique for memory application has been proposed. In this paper we are encoding the 1 bit data into 16 bit data and storing it into a memory of certain address location given by the linear feedback shift register (LFSR), whose input is taken from the pseudo random sequence generator (PRSG). The encoded 16 bit data is stored into memory controller, the encoded data is decoded back into 1 bit data under the condition when MSB bit is at logic state 1. By using FM0/Manchester encoding and decoding technique, the data will be secure, this process is easy and faster to carry out. This paper develops a fully reused VLSI architecture, and also exhibits an efficient performance.

Keywords: FM0/ Manchester encoder, Linear feedback shift register LFSR, Pseudo random sequence generator PRSG, Memory controller

Edition: Volume 4 Issue 5, May 2015,

Pages: 865 - 868